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1 ? fn6450.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL12020 real time clock with on chip temp compensation 5ppm low power rtc with v dd battery backed sram and embedded temp compensation 5 ppm with auto day light saving the ISL12020 device is a low power real time clock with an embedded temp sensor for oscillator compensation, clock/calendar, power fail, low battery monitor, brown out indicator, single periodic or polled alarms, intelligent battery backup switching and 128 bytes of battery-backed user sram. the oscillator uses an external, low-cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. daylight savings time adjustment is done automatically, using parameters entered by the user. power fail and battery monitors offer user-selectable trip levels. a time stamp function records the time and date of switchover from v dd to battery power, and also from battery to v dd power. pinout ISL12020 (8 ld soic) top view features ? real time clock/calendar - tracks time in hours, minutes and seconds - day of the week, day, month and year ? on-chip oscillator compensa tion over the operating te m p r a n g e - 5ppm over -20c to +70c ? day light saving time - customer programmable ? 15 selectable frequency outputs ? 1 alarm - settable to the second, minute, hour, day of the week, day, or month - single event or pulse interrupt mode ? automatic backup to battery or super cap - operation to v bat = 1.8v - 1.0a battery supply current ? battery status monitor, 2 levels, selectable by customer to: - seven selectable voltages for each level ? power status brown out monitor ? six selectable trip level, from 4.675v to 2.295v power failure detection ? time stamp during power to battery and battery to power cross over - time stamp. first v dd to v bat , and last v bat to v dd ? 128 bytes batter y-backed user sram ?i 2 c interface - 400khz clock frequency ? 8 ld soic package ISL12020 ? pb-free plus anneal available (rohs compliant) applications ? utility meters ? pos equipment ? medical application ? security related application ? vending machine ? white goods data sheet vdd irq /f out scl sda x1 x2 vbat 1 2 3 4 8 7 6 5 gnd march 29, 2007
2 fn6450.0 march 29, 2007 block diagram ordering information part number (note) part marking v dd range temp range (c) package (pb-free) pkg dwg # future product ISL12020ibz* 12020 ibz 2.7v to 5.5v -40 to +85 8 ld soic m8.15 ISL12020cbz* 12020 cbz 2.7v to 5.5v -20 to +70 8 ld soic m8.15 *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. i 2 c interface control logic alarm frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl x1 x2 v dd v bat irq / f out internal supply v trip seconds minutes hours day of week date month year user sram control registers gnd registers temperature sensor frequency control pin descriptions pin number symbol description 1x1 x1. the x1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x1 can also be driven directly from a 32.768khz source. 2x2 x2. the x2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quartz crystal. x2 should be left open when x1 is driven from external source. 3 vbat vbat. this input provides a backup s upply voltage to the device. v bat supplies power to the dev ice in the event that the v dd supply fails. this pin shoul d be tied to ground if not used. 4gnd ground . 5sda serial data ( sda ). sda is a bi-directional pin used to transfer seri al data into and out of the device. it has an open drain output and may be wire or?ed with other open drain or open collector outputs. 6scl serial clock ( scl ). the scl input is used to clock all serial data into and out of the device. 7irq /fout interrupt output irq , /frequency output fout. multi-functional pin that can be used as interrupt or frequency output pin. the function is set via the configuration register. 8vdd vdd. power supply. ISL12020
3 fn6450.0 march 29, 2007 absolute maximum rati ngs thermal information voltage on vdd, vbat, scl, sda, and irq /f out pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on x1 and x2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.5v esd rating human body model (per mil-std-883 method 3014) . . . . .>2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150v thermal resistance (typical, note 1) ja (c/w) 8 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. dc operating char acteristics-rtc test conditions: v dd = +2.7 to +5.5v, temperature = -20c to +70c, unless otherwise stated. symbol parameter conditions min typ (note 7) max units notes v dd main power supply 2.7 5.5 v v bat battery supply voltage 1.8 5.5 v 2 i dd1 supply current v dd = 5v 4.1 6.5 a 3, 5 v dd = 3v 3.5 5.5 a 3, 5 i dd2 supply current (i 2 c communications active) v dd = 5v 300 500 a 3, 4 i dd3 supply current (temperature conversion active) v dd = 5v 250 400 a 3, 4 i bat battery supply current v bat = 3v @ +25c 1.0 1.6 a 3 v bat = 3v 1.0 2.1 a 3 i batlkg battery input leakage v dd = 5.5v, v bat = 1.8v 100 na i li input leakage current on scl 100 na 4 i lo i/o leakage current on sda 100 na 4 v batm battery level monitor threshold -100 +100 mv v pbm brown out level monitor threshold -100 +100 mv v trip v bat mode threshold 2.1 2.2 2.6 v v triphys v trip hysteresis 10 30 50 mv v bathys v bat hysteresis 50 mv 9 frequency stability vs temperature 2.7v v dd 3.6v, 5 ppm 9 frequency stability vs voltage 2.7v v dd 3.6v 3 ppm 9 atr sensitivity per lsb beta (3:0) = 1000 1 ppm 9 temperature sensor accuracy v dd = v bat = 3.3 v 3 c 9 irq /f out v ol output low voltage v dd = 5v, i ol = 3ma 0.4 v v dd = 2.7v, i ol = 1ma 0.4 v power-down timing test conditions: v dd = +2.7 to +5.5v, temperature = -20c to +70c, unless otherwise stated. symbol parameter conditions min typ (note 7) max units notes v dd sr- v dd negative slew rate 10 v/ms 8 ISL12020
4 fn6450.0 march 29, 2007 i 2 c interface specifications test conditions: v dd =+2.7 to +5.5v, temperature = -20c to +70c, unless otherwise specified. symbol parameter test conditions min typ (note 7) max units notes v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v v ol sda output buffer low voltage, sinking 3ma v dd = 5v, i ol = 3ma 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 0 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns ISL12020
5 fn6450.0 march 29, 2007 t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0ns t r sda and scl rise time from 30% to 70% of v dd. 20 + 0.1 x cb 300 ns t f sda and scl fall time from 70% to 30% of v dd. 20 + 0.1 x cb 300 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2~2.5k . for cb = 40pf, max is about 15~20k 1k notes: 2. temperature conversion is inactive below 2.7v v bat 3. irq/ f out inactive. 4. v il = v dd x 0.1, v ih = v dd x 0.9, f scl = 400khz 5. v dd > v bat +v bathys 6. bit bsw = 0 (standard mode), v bat 1.8v 7. specified at +25c. 8. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 9. parameter is not 100% tested. 10. these are i 2 c specific parameters and are not tested, however, they are used to set conditions for testing dev ices to validate specificatio n. i 2 c interface specifications test conditions: v dd =+2.7 to +5.5v, temperature = -20c to +70c, unless otherwise specified. (continued) symbol parameter test conditions min typ (note 7) max units notes ISL12020
6 fn6450.0 march 29, 2007 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ISL12020
7 fn6450.0 march 29, 2007 general description the ISL12020 devi ces are low power real time clocks (rtcs) with embedded temperat ure sensors. they contain crystal frequency compensation ci rcuitry over the operating temperature range, clock/calendar, power fail and low battery monitors, brown out indicator with separate (lvrset ) reset pin (isl12021 only), 1 periodic or polled alarm, intelligent battery back up switching and 128 bytes of battery-backed user sram. the oscillator uses an external, low cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. in addition, both the ISL12020 could be programmed for automatic daylight saving time (dst) adjustment by entering local dst information. the isl1202x?s alarm can be set to any clock/calendar value for a match. for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register, or the device can be configured to provide a hardware interrupt via the irq pin. there is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. the device also offers a backup power input pin. this v bat pin allows the device to be backed up by battery or super cap with automatic switchover from v dd to v bat . the ISL12020 devices are specified for v dd = 2.7v to 5.5v and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8v (standby mode). the v bat level is monitored and reported against preselected levels. the first report is registered when the v bat level falls below 85% of nominal level, the second level is set for 75%. battery levels are stored in v batm registers. the ISL12020 offers a ?brown out? alarm once the v dd falls below a pre-selected trip level. in the ISL12020, this allows system micro to save vital information to memory before complete power loss. there are six v dd levels that could be selected for initiation of brown out alarm. pin descriptions x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal is used with the device to supply a timebase for the real time clock. internal compensation circuitry with internal temperature sensor provides frequency corrections for selected popular crystals to 5ppm over the operating temperature range from -40c t o +85c. (see ?application section? on page 22 for recommended crystal). ISL12020 allows the user to input via i2c serial bus the temperature variation profile of crystals not listed in the ?application section? on page 22. this oscillator compensation network can also be used to calibrate the initial crystal timing accuracy at room temperature. the device can also be driven directly from a 32. 768khz source at pin x1. vbat this input provides a backup supply voltage to the device. vbat supplies power to the device in the event that the vdd supply fails. this pin can be connected to a battery, a super capacitor or tied to ground if not used. see the battery monitor parame ter in the dc operating characteristics-rtc on page 3. irq /f out (interrupt output/frequency output) this dual function pin can be used as an interrupt or frequency output pin. the irq /f out mode is selected via the frequency out control bits of the control/status register. ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low output. ? frequency output mode. the pin outputs a clock signal which is related to the crystal frequency. the frequency output is user selectable and enabled via the i 2 c bus. it is an open drain output. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). it is disabled when the backup power supply on the v bat pin is activated to minimize power consumption. figure 1. standard output load for testing the device with v dd = 5.0v sda and irq /fout 1533 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circuit for v dd = 5v figure 2. recommended crystal connection x1 x2 ISL12020
8 fn6450.0 march 29, 2007 serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it has an open drain output and may be ored with other open drain or open co llector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor. the output circuitry controls the fa ll time of the output signal with the use of a slope contro lled pull-down. the circuit is designed for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the v bat pin is activated. vdd, gnd chip power supply and ground pins. the device will operate with a power supply from vdd = 2.7v to 5.5vdc. a 0.1f capacitor is recommended on the vdd pin to ground. functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the isl1202x for up to 10 years. another option is to use a super capacitor for applications where v dd is interrupted for up to a month. see the ?application section? on page 22 for more information. normal mode (v dd ) to battery backup mode (v bat ) to transition from the vdd to vbat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys 50mv condition 2: v dd < v trip where v trip 2.2v battery backup mode (v bat ) to normal mode (v dd ) the ISL12020 device will switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys 50mv condition 2: v dd > v trip + v triphys where v triphys 30mv these power control situations are illustrated in figure 3 and figure 4. the i 2 c bus is deactivated in battery backup mode to reduce power consumption. aside from this, all rtc functions are operational during battery backup mode. except for scl and sda, all the inputs and outputs of the ISL12020 are active during battery backup mode unless disabled via the control register. the device time stamps the switchover from v dd to v bat and v bat to v dd , and the time is stored in t sv2b and t sb2v registers respectively. if multiple v dd power down sequences occur before status is read, the earliest v dd to v bat power down time is stored and the most recent v bat to v dd time is stored. temperature conversion and compensation can be enabled in battery backup mode. bit btse in the beta register controls this operation as descr ibed in that register section. power failure detection both the ISL12020 provide a real time clock failure bit (rtcf) to detect total power failure. it allows users to determine if the device has powered up after having lost all power to the device (both v dd and v bat ). brownout detection the ISL12020 monitor the v dd level continuously and provide warning if the v dd level drops below prescribed levels. there are six (6) levels that can be selected for the trip level. these values are 85% below popular v dd levels. the lvdd bit in the status register will be set to ?1? when brownout is detected. note. the i 2 c serial bus remains active unless the battery vtrip levels are reached. v bat - v bathys v bat v bat + v bathys battery backup mode v dd v trip 2.2v 1.8v figure 3. battery switchover when v bat < v trip figure 4. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v ISL12020
9 fn6450.0 march 29, 2007 battery level monitor the ISL12020 have a built in warning feature once the back up battery level drops first to 85% and then to 75% of the battery?s nominal vbat level. when the battery voltage drops to between 85% and 75%, the lbat85 bit is set in the status register. when the level drops below 75%, both lbat85 and lbat75 bits are set in the status register. there is a battery timestamp function available. once the v dd is low enough to enable switchover to the battery, the rtc time/date are written into the tsvtb register. this information can be read from the tsvtb registers to discover the point in time of the v dd powerdown. if there are multiple powerdown cycles befor e reading these registers, the first values stored in t hese registers will be retained. these registers will hold the original powerdown value until they are cleared by writing ?00h? to each register. low power mode the normal power switching of the ISL12020 is designed to switch into battery backup mode only if the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. another mode (called low power mode) is available to allow direct switching from v dd to v bat without requiring v dd to drop below v trip . since the additional monitoring of v dd vs v trip is no longer needed, that circuitry is shut down and less power is used while operating from v dd . power savings are typically 600na at v dd = 5v. low power mode is activated via the bsw bit in the control and status registers. low power mode is useful in systems where v dd is normally higher than v bat at all times. the dev ice will switch from v dd to v bat when v dd drops below v bat , with about 50mv of hysteresis to prevent any switchback of v dd after switchover. in a system with v dd = 5v and backup lithium battery of v bat = 3v, low power mode can be used. however, it is not recommended to use low power mode in a system with v dd = 3.3v 10%, v bat 3.0v, and when there is a finite i-r voltage drop in the v dd line. real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. the rtc also has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or am/pm format. when the ISL12020 powers up after the loss of both v dd and v bat , the clock will not begin incrementing until at least one byte is written to the clock register. single event and interrupt the alarm mode is enabled via the msb bit. choosing single event or interrupt alarm mode is selected via the im bit. note that when the frequency output function is enabled, the alarm function is disabled. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occurs in single event mode, an irq pin will be pulled low and the alarm status bit (alm) will be set to ?1?. the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). during pulsed interrupt mode, the irq pin will be pulled low for 250ms and the alarm status bit (alm) will be set to ?1?. the alm bit can be reset by the user or cleared automatically using the auto reset mode (see arst bit). the alarm function can be enabled/disabled during battery backup mode using the fobatb bit. for more information on the alarm, please see ?alarm registers (10h to 15h)? on page 17. frequency output mode the ISL12020 has the option to provide a clock output signal using the irq /fout open drain output pin. the frequency output mode is set by using the fo bits to select 15 possible output frequency values from 1/32hz to 32khz. the frequency output can be enabled/disabled during battery backup mode using the fobatb bit. general purpose user sram the ISL12020 provides 128 bytes of user sram. the sram will continue to operate in battery backup mode. however, it should be noted that the i 2 c bus is disabled in battery backup mode. i 2 c serial interface the ISL12020 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). oscillator compensation the ISL12020 provides both initial timing correction and temperature correction due to variation of the crystal oscillator. analog and digital trimming control is provided for initial adjustment, and a temp erature compensation function is provided to automatically correct for temperature drift of the crystal. initial values fo r the temperature coefficient (alpha) and crystal capacitance (beta) are required for best accuracy. the function can be enabled/disabled at any time and can be used in battery mode as well. ISL12020
10 fn6450.0 march 29, 2007 register descriptions the battery-backed registers are accessible following a slave byte of ?1101111x? and reads or writes to addresses [00h:13h]. the defined addresses and default values are described in the table 1. the battery backed general purpose sram has a different slave address (1010111x), so it is not possible to read/writ e that section of memory while accessing the registers. register access the contents of the register s can be modified by performing a byte or a page write operation directly to any register address. the registers are divided into 8 sections. they are: 1. real time clock (7 bytes): address 00h to 06h. 2. control and status (9 bytes): address 07h to 0fh. 3. alarm (6 bytes): address 10h to 15h. 4. time stamp for battery status (5 bytes): address 16h to 1ah. 5. time stamp for vdd status (5 bytes): address 1bh to 1fh. 6. day light saving time (8 bytes): 20h to 27h. 7. temp (2 bytes): 28h to 29h 8. scratch pad (6 bytes): address 2ah to 2fh. write capability is allowable into the rtc registers (00h to 06h) only when the wrtc bit (bit 6 of address 08h) is set to ?1?. a multi-byte read or write operation is limited to one section per operation. access to another section requires a new operation. a read or wr ite can begin at any address within the section. a register can be read by performing a random read at any address at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. for the rtc a nd alarm registers, the read instruction latches all clock r egisters into a buffer, so an update of the clock does not change the time being read. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the address remains at the previous addre ss +1 so the user can execute a current address read and continue reading the next register. it is not necessary to set the wrtc bit prior to writing into the control and status, alarm, and user sram registers. ISL12020
11 fn6450.0 march 29, 2007 table 1. register memory map addr. section reg name bit range default 76543210 00h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 00h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 01h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 01h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 06h dw00000dw2dw1dw00 to 600h 07h csr sr busy oscf dstadj alm lvdd lbat85 lbat75 rtcf n/a 01h 08h int arst wrtc im fobatb fo3 fo2 fo1 fo0 n/a 00h 09h pwr_vdd clrts d d d d v dd trip2 v dd trip1 v dd trip0 n/a 00h 0ah pwr_vbat bsw d vb85tp2 vb85tp1 vb85tp0 vb75tp2 vb75tp1 vb75tp0 n/a 00h 0bh itro idtr01 idtr00 iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 n/a 08h 0ch alpha d alpha6 alpha5 alpha4 alpha3 alpha2 alpha1 alpha0 n/a 25h 0dh beta tse btse btsr d beta3 beta2 beta1 beta0 n/a 08h 0eh fatr 0 0 ffatr5 fatr4 fatr3 fatr2 fatr1 fatr0 n/a 00h 0fh fdtr00000fdtr2fdtr1fdtr0n/a00h 10h alarm sca0 esca0 sca022 sca021 sca020 sca013 sca012 sca011 sca010 00 to 59 00h 11h mna0 emna0 mna022 mna021 mna020 mna013 mna012 mna011 mna010 00 to 59 00h 12h hra0 ehra0 d hra021 hra020 hra013 hra012 hra011 hra010 0 to 23 00h 13h dta0 edta0 d dta021 dta020 dta013 dta012 dta011 dta010 01 to 31 01h 14h moa0 emoa00 d d moa020 moa013 moa012 moa011 moa010 01 to 12 01h 15h dwa0 edwa0 d d d d dwa02 dwa01 dwa00 0 to 6 00h 16h tsv2b vsc 0 vsc22 vsc21 vsc20 vsc13 vsc12 vsc11 vsc10 0 to 59 00h 17h vmn 0 vmn22 vmn21 vmn20 vmn13 vmn12 vmn11 vmn10 0 to 59 00h 18h vhr vmil 0 vhr21 vhr20 vhr13 vhr12 vhr11 vhr10 0 to 23 00h 19h vdt 0 0 vdt21 vdt20 vdt13 vdt12 vdt11 vdt10 1 to 31 00h 1ah vmo 0 0 0 vmo20 vmo13 vmo12 vmo11 vmo10 1 to 12 00h 1bh tsb2v bsc 0 bsc22 bsc21 bsc20 bsc13 bsc12 bsc11 bsc10 0 to 59 00h 1ch bmn 0 bmn22 bmn21 bmn20 bmn13 bmn12 bmn11 bmn10 0 to 59 00h 1dh bhr bmil 0 bhr21 bhr20 bhr13 bhr12 bhr11 bhr10 0 to 23 00h 1eh bdt 0 0 bdt21 bdt20 bdt13 bdt12 bdt11 bdt10 1 to 31 00h 1fh bmo 0 0 0 bmo20 bmo13 bmo12 bmo11 bmo10 1 to 12 00h ISL12020
12 fn6450.0 march 29, 2007 20h dstcr dstmofd dste d d dstmofd20 dstmofd13 dstmofd12 dstmofd11 dstmofd10 1 to 12 00h 21h dstdwfd dstdwefd d d d d dstdwfd12 dstdwfd11 dstdwfd10 0 to 6 00h 22h dstdtfd d d dstdtfd21 dstdtfd20 dstdtfd13 dstdtfd12 dstdtfd11 dstdtfd10 1 to 31 00h 23h dsthrfd d d dsthrfd21 dsthrfd20 dsthrfd13 dsthrfd12 dsthrfd11 dsthrfd10 0 to 23 00h 24h dstmorv d d d xdstmorv2 0 dstmorv13 dstmor12v dstmorv11 dstmorv10 01 to 12 00h 25h dstdwrv dstdwerv d d d d dstdwrv12 dstdwrv11 dstdwrv10 0 to 6 00h 26h dstdtrv d d dstdtrv21 dstdtrv20 dstdtrv13 dstdtrv12 dstdtrv11 dstdtrv10 01 to 31 00h 27h dsthrrv d d dsthrrv21 dsthrrv20 dsthrrv13 dsthrrv12 dsthrrv11 dsthrrv10 0 to 23 00h 28h temp tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 00 to ff 00h 29h tk0m000000tk09tk0800 to 0300h 2ah gpm gpm1 gpm17 gpm16 gpm15 gpm14 gpm13 gpm12 gpm11 gpm10 00 to ff 00h 2bh gpm2 gpm27 gpm26 gpm25 gpm24 gpm23 gpm22 gpm21 gpm20 00 to ff 00h 2ch gpm3 gpm37 gpm36 gpm35 gpm34 gpm33 gpm32 gpm31 gpm30 00 to ff 00h 2dh gpm4 gpm47 gpm46 gpm45 gpm44 gpm43 gpm42 gpm41 gpm40 00 to ff 00h 2eh gpm5 gpm57 gpm56 gpm55 gpm54 gpm53 gpm52 gpm51 gpm50 00 to ff 00h 2fh gpm6 gpm67 gpm66 gpm65 gpm64 gpm63 gpm62 gpm61 gpm60 00 to ff 00h table 1. register memory map (continued) addr. section reg name bit range default 76543210 ISL12020
13 fn6450.0 march 29, 2007 real time clock registers addresses [00h to 06h] rtc registers (sc, mn, hr, dt, mo, yr, dw) these registers depict bcd repr esentations of the time. as such, sc (seconds) and mn (minutes) range from 0 to 59, hr (hour) can either be a 12-hour or 24-hour mode, dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99, and dw (day of the week) is 0 to 6. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2-? the assignment of a numeri cal value to a specific day of the week is arbitrary a nd may be decided by the system software designer. the default value is defined as ?0?. 24 hour time if the mil bit of the hr register is ?1?, the rtc uses a 24-hour format. if the mil bit is ?0?, the rtc uses a 12-hour format and hr21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to 12-hour format time with hr21 = ?0?. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. ye ars divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year and the year 2100 is not. the ISL12020 does not correct for the leap year in the year 2100. control and status registers (csr) addresses [07h to 0fh] the control and status regist ers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) the status register is located in the memory map at address 07h. this is a volatile register that provides either control or status of rtc failure (rtcf), battery level monitor (lbat85, lbat75), alarm trigger, daylight saving time, crystal oscillator enable and temperature conversion in progress bit. busy bit (busy) busy bit indicates temperature sensing is in progress. in this mode, alpha, beta and itro registers are disabled and cannot be accessed. oscillator fail bit (oscf) indicates oscillator stopped. daylight saving time change bit (dstadj) dstadj is the daylight saving time adjusted bit. it indicates the daylight saving time adjustment has happened. dstadj is reset to 0 upon power up. if dst event happens (at either the beginning or the end of dst), dstadj will be set to 1. a read of the sr will reset the dstadj, or it will be automatically reset on the following month. alarm bit (alm) these bits announce if the alarm matches the real time clock. if there is a match, the respective bit is set to ?1?. this bit can be manually reset to ?0? by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. low v dd indicator bit (lv dd vdd) indicates v dd dropped below the pre-selected trip level. (brown out mode). the trip points for brown out levels are selected by three bits v dd trip2, v dd trip1 and v dd trip0 in pwr_v dd registers. low battery indicator 85% bit (lbat85) indicates battery level dropped below the pre-selected trip levels (85% of battery voltage). the trip points are selected by three bits: vb85tp2, vb85tp1 and vb85tp0 in the pwr_vbat registers. low battery indicator 75% bit (lbat75) indicates battery level dropped below the pre-selected trip levels (75% of battery voltage). the trip points are selected by three bits vb75tp2, vb75tp1 and vb75tp0 in the pwr_vbat registers. real time clock fail bit (rtcf) this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardware (ISL12020 internally) when the device powers up after having lost all power (defined as v dd = 0v and v bat = 0v). the bit is set regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (w riting one byte is sufficient). interrupt control register (int) automatic reset bit (arst) this bit enables/disables the automatic reset of the alm, lvdd, lbat85, and lbat75 status bits only. when arst bit is set to ?1?, these status bits are reset to ?0? after a valid read of the respective status register (with a valid stop table 2. status register (sr) addr 7 6 5 4 3 2 1 0 07h busy oscf dstdj alm lvdd lbat85 lbat75 rtcf table 3. interrupt control register (int) addr7 6 5 4 3210 08h arst wrtc im fobatb fo3 fo2 fo1 fo0 ISL12020
14 fn6450.0 march 29, 2007 condition). when the arst is cleared to ?0?, the user must manually reset the alm, lvdd, lbat85, and lbat75 bits. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc timing registers. the factor y default setting of this bit is ?0?. upon initialization or power up, the wrtc must be set to ?1? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc internal 1hz signal is synchronized to the stop condition during a valid write cycle. interrupt/alarm mode bit (im) this bit enables/disables the interrupt mode of the alarm function. when the im bit is set to ?1?, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq /f out pin when the rtc is triggered by the alarm as defined by the alarm registers (0ch to 11h). when the im bit is cleared to ?0?, the alarm will operate in standard mode, where the irq /fout pin will be set low until the alm status bit is cleared to ?0?. frequency output and interrupt bit (fobatb) this bit enables/disables the fout/irq pin during battery backup mode (i.e. v bat power source active). when the fobatb is set to ?1? the fout/irq pin is disabled during battery backup mode. this means that both the frequency output and alarm output func tions are disabled. when the fobatb is cleared to ?0?, the fout/irq pin is enabled during battery backup mode. note that the open drain fout/irq pin will need a pullup to the battery voltage to operate in battery backup mode. frequency out control bits (fo <3:0>) these bits enable/disable the frequency output function and select the output frequency at the irq /fout pin. see table 5 for frequency selection. when the frequency mode is enabled, it will override the alarm mode at the irq /fout pin. power supply control register (pwr_vdd) clear time stamp bit (clrts) this bit clears time stamp v dd to battery (tsv2b) and time stamp battery to v dd registers (tsb2v). the default setting is 0 (clrts = 0) and the enabled setting is 1 (clrts = 1) v dd brown out trip voltage bits (vddtrip)<2:0 these bits set the 6 trip levels for the v dd alarm, indicating that v dd has dropped below a preset le vel, in this event, the lvdd bit in the status register is set to ?1?. see table 6. battery voltage trip voltage register (pwr_vbat) this register controls the trip points for the two vbat alarms, with levels set to approximately 85% and 75% of the nominal battery level. table 4. im bit interrupt/alarm frequency 0 single time event set by alarm 1 repetitive/recurring time event set by alarm table 5. frequency selection of fout pin frequency, fout units fo3 fo2 fo1 fo0 0 hz0 000 32768 hz 0 0 0 1 4096 hz 0 0 1 0 1024 hz 0 0 1 1 64 hz0 100 32 hz0 101 16 hz 0 1 1 0 8hz0111 4hz1000 2hz1001 1hz1010 1/2 hz 1 0 1 1 1/4 hz 1 1 0 0 1/8 hz 1 1 0 1 1/16 hz 1 1 1 0 1/32 hz 1 1 1 1 addr 7 6543 2 1 0 09h clrts 0 0 0 0 v dd trip2 v dd trip1 v dd trip0 table 6. vdd trip levels v dd trip2 v dd trip1 v dd trip0 trip voltage (v) 0 0 0 2.295 0 0 1 2.550 0 1 0 2.805 0 1 1 3.060 1 0 0 4.250 1 0 1 4.675 table 7. addr 7 6 543210 0ah bsw 0 vb85 tp2 vb85 tp1 vb85 tp0 vb75 tp2 vb75 tp1 vb75 tp0 table 5. frequency selection of fout pin (continued) frequency, fout units fo3 fo2 fo1 fo0 ISL12020
15 fn6450.0 march 29, 2007 battery switchover bit (bsw) this bit selects either standard mode or low power mode battery switchover. in standard mode (bsw = 0), the v dd switches over to battery at the lo w trip point, typically 2.2v. in low power mode (bsw = 1), v dd switches over to battery at the battery voltage (v bat ). low power mode uses less power in battery backup for applications requiring longer backup times. battery level monitor tr ip bits (vb85tp <2:0>) three bits selects the first alarm (85% of nominal vbat) level for the battery voltage monitor. there are total of 7 levels that could be selected for the first alar m.any of the of levels could be selected as the first alarm with no reference as to nominal battery voltage level. see table 8. battery level monitor tr ip bits (vb75tp <2:0>) three bits selects the second alarm (75% of nominal vbat) level for the battery voltage monitor. there are total of 7 levels that could be selected for the second alarm. any of the of levels could be selected as the second alarm with no reference as to nominal battery voltage level. see table 9. initial atr and dtr setting register (itro) these bits are to be used to trim the initial error (at room temperature) of the crystal. both digital (dtr) and analog (atr) trimming methods are available. the digital trimming uses clock pulse skipping and insertion for frequency adjustment. analog trimming uses load capacitance adjustment to pull the oscillator frequency. a range of +64ppm to -63ppm is possible with combined digital and analog trimming. aging and initial trim digital trimming bits (idtr0) <2:0> these bits allow 32ppm initial trimming range for the crystal frequency. this is meant to be a coarse adjustment if the range needed is outside that of the iatr control. see table 10. the idtr0 register should only be changed while the tse (temp sense enable) bit is ?0?. aging and initial analog trimming bits (iatr0)<6:0> the analog trimming register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. this enables fine frequency adjustment for trim ming initial crystal accuracy error or to correct for aging drift. the iatr0 register should only be changed while the tse (temp sense enable) bit is ?0?. table 8. vb85t alarm level vb85tp2 vb85tp1 vb85tp0 battery alarm trip level (v) 0 0 0 2.125 0 0 1 2.295 0 1 0 2.550 0 1 1 2.805 1 0 0 3.060 1 0 1 4.250 1 1 0 4.675 table 9. battery level monitor trip bits (vb75tp <2:0>) vb75tp2 vb75tp1 vb75tp0 battery alarm trip level (v) 0 0 0 1.875 0 0 1 2.025 0 1 0 2.250 0 1 1 2.475 1 0 0 2.700 1 0 1 3.750 1 1 0 4.125 table 10. idtr0 trimming range idtr01 idtr00 trimming range 0 0 default /disabled 0 1 +32ppm 1 0 0ppm 1 1 -32ppm table 11. initial atr and dtr setting register addr7 6543210 0bh idtr01 idtr00 iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 table 12. iatro trimming range iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range 000000 +32 000001 +31 000010 +30 000011 +29 000100 +28 000101 +27 000110 +26 000111 +25 001000 +24 001001 +23 001010 +22 001011 +21 ISL12020
16 fn6450.0 march 29, 2007 alpha register (alpha) the alpha variable is 7 bits and is defined as the temperature coefficient of crystal, normally given in units of ppm/c 2 = and with a typical value of -0.034. the ISL12020 devices use a scaled version of the absolute value of this coefficient in order to get an integer value. therefore, alpha <6:0> is defined as the (|actual alpha value| x 1024) and converted to binary. for example, a crystal with alpha of - 0.034ppm/c 2 is first scaled: |1024*(-0.034)| = 35d and then converted to a binary number of 0100011b. the practical range of actual alpha values is from -0.020 to -0.060. the alpha register should only be changed while the tse (temp sense enable) bit is ?0?. beta register (beta) temperature sensor enabled bit (tse) this bit enables the temperature sensing operation, including the temperature sensor, a/d c onverter and atr/dtr register adjustment. the default mode after power up is disabled (tse = 0). to enable the operation, tse should be set to 1 (tse = 1). when temp sense is disabled, the initial values for iatr and idtr registers are used for frequency control. all changes to the idtr, iatr, alpha and beta registers must be made with tse = 0. after loading the new values, then tse can be enabled and the new values are used. temp sensor conversion in battery mode bit (btse) this bit enables the temperature sensing and correction in battery mode. btse = 0 defual t no conversion in battery mode. btse = 1 temp sensing enabled in battery mode.the btse is disabled when battery voltage is lower than 2.6v. frequency of temperature sensing and correction bit (btsr) this bit controls the frequency of temp sensing and correction. btsr = 0 default mode is every 10 minutes, btsr = 1 is every 1.0 minute. note that btse has to be enabled in both cases. see table 15. 001100 +20 001101 +19 001110 +18 001111 +17 010000 +16 010001 +15 010010 +14 010011 +13 010100 +12 010101 +11 010110 +10 010111 +9 011000 +8 011001 +7 011010 +6 011011 +5 011100 +4 011101 +3 011110 +2 011111 +1 100000 0 100001 -1 100010 -2 100011 -3 100100 -4 100101 -5 100110 -6 100111 -7 101000 -8 101001 -9 101010 -10 101011 -11 101100 -12 101101 -13 101110 -14 101111 -15 110000 -16 110001 -17 110010 -18 110011 -19 110100 -20 110101 -21 110110 -22 110111 -23 111000 -24 111001 -25 111010 -26 111011 -27 111100 -28 111101 -29 111110 -30 111111 -31 table 12. iatro trimming range (continued) iatr05 iatr04 iatr03 iatr02 iatr01 iatr00 trimming range table 13. alpha register addr 7 6 5 4 3210 0ch 0 alpha6 alpha5 alpha4 alpha3 alpha2 alpha1 alpha0 table 14. addr 7 6 5 4 3210 0dh tse btse btsr 0 beta3 beta2 beta1 beta0 ISL12020
17 fn6450.0 march 29, 2007 gain factor of atr bit (beta)<3:0> beta is specified to take care of the cm variations of the crystal. most crystals specify cm around 2.2ff. for example, if cm > 2.2ff, the actual atr steps may reduce from 1ppm/step to approximately 0.8 0ppm/step. beta is then used to adjust for this variation and restore the step size to 1ppm/step. the value for beta should only be changed while the tse (temp sense enable) bit is ?0?. the procedure for writing the beta register involves two steps. first, write the new value of beta with tse = 0. then wr ite the same value of beta with tse = 1. this will insure the next temp sense cycle will use the new beta value. beta values are limited in the range from 0100 to 1100 as shown in table 16 . final analog trimming register (fatr) this register shows the final setting of atr after temperature correction. it is read-only, the user cannot overwrite a value to this register. this value is accessible as a means of monitoring the temperature compensation function. see table 17. final digital trimmi ng register (fdtr) this register shows the final setting of dtr after temperature correction. it is read-only, the user cannot overwrite a value to this register. the value is accessible as a means of monitoring the temperature compensation function. the corresponding cl ock adjustment values are shown in table 19. the dtr setting is only positive as it is used to correct for the negative drift of a normal crystal over temperature. alarm registers (10h to 15h) the alarm register bytes are set up identical to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc registers. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers an d the rtc registers. any one alarm register, multiple registers, or all registers can be enabled for a match. there are two alarm operation modes: single event and periodic interrupt mode: ? single event mode is enabled by setting the bit 7 on any of the alarm registers (esca0. .. edwa0) to ?1?, the im bit to ?0?, and disabling the frequency output. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm bit is set to ?1? and the irq output will be pulled low and will remain low until the alm bit is reset. this can be done manually or by using the auto-reset feature. ? interrupt mode is enabled by setting the bit 7 on any of the alarm registers (esca0... ed wa0) to ?1?, the im bit to table 15. frequency of temperature sensing and correction bit btse btsr tc period in battery mode 00off 01off 1 0 10 minutes 1 1 1 minute table 16. beta values beta<3:0> atr step adjustment 0100 0.500 0101 0.625 0110 0.750 0111 0.875 1000 1.00 1001 1.125 1010 1.250 1011 1.375 1100 1.500 table 17. final analog trimming register addr76543210 0eh 0 0 fatr5 fatr4 fatr3 fatr2 fatr1 fatr0 table 18. final digital trimming register addr 76543 2 1 0 0fh fdtr2 fdtr1 fdtr0 table 19. clock adjustment values for final digital trimming register dtr<2:0> decimal ppm adjustment 000 0 0 001 1 32 010 2 64 011 3 96 100 4 128 101 5 160 110 6 196 111 7 -32 ISL12020
18 fn6450.0 march 29, 2007 ?1?, and disabling the frequency output. the irq output will now be pulsed each time an alarm occurs. this means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. to clear a single event alarm, the alm bit in the status register must be set to ?0? with a write. note that if the arst bit is set to 1 (address 08h, bit 7), the alm bit will automatically be cleared when the status register is read. following are examples of both single event and periodic interrupt mode alarms. example 1 ? alarm set with single interrupt (im = ?0?) ? a single alarm will occur on january 1 at 11:30am. ? set alarm registers as follows: after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30am on january 1 (after seconds changes from 59 to 00) by setting the alm bit in the status register to ?1? and also bringing the irq output low. example 2 ? pulsed interrupt once per minute (im = ?1?) ? interrupts at one minute intervals when the seconds register is at 30 seconds. ? set alarm registers as follows: once the registers are set, the following waveform will be seen at irq: note that the status register alm bit will be set each time the alarm is triggered, but does not need to be read or cleared time stamp v dd to battery registers (tsv2b) the tsv2b register bytes are identical to the rtc register bytes, except they do not extend beyond the month. the time stamp captures the first v dd to battery voltage transition time, and will not update upon subsequent events, until cleared (only the first event is captured before clearing). set clrts = 1 to clear this register (add 09h, pwr_v dd register). note that the time stamp registers are cleared to all ?0?, including the month and day, wh ich is different from the rtc and alarm registers (those regist ers default to 01h). this is the indicator that no time stamping has occurred since the last clear or initial powerup. on ce a time stamp occurs, there will be a non-zero time stamp. time stamp battery to v dd registers (tsb2v) the time stamp battery to v dd register bytes are identical to the rtc register bytes, exce pt they do not extend beyond month. the time stamp captur es the last transition of v bat to v d (only the last event of a series of power up/down events is retained). set clrts = 1 to clear this register (add 09h, pwr_v dd register). dst control registers (dstcr) 8 bytes of control registers have been assigned for the daylight savings time (dst) functions. dst beginning time is controlled by the register s dstmofd, dstdwfd, dstdtfd alarm register bit description 76543210hex sca0 00000000 00hsec onds disabled mna0 10110000 b0hminutes set to 30, enabled hra0 10010001 91hhours set to 11, enabled dta0 10000001 81hdate set to 1, enabled moa0 10000001 81hmonth set to 1, enabled dwa0 00000000 00hday of week disabled alarm register bit description 76543210hex sca0 10110000b0hseconds set to 30, enabled mna0 00000000 00hminutes disabled hra0 00000000 00hhours disabled dta0 00000000 00hdate disabled moa0 00000000 00hmonth disabled dwa0 00000000 00hday of week disabled alarm register bit description 76543210hex 60s rtc and alarm registers are both ?30s? figure 5. irq waveform bmode clrts clrts int+ v dd ts v bat ts figure 6. ISL12020
19 fn6450.0 march 29, 2007 and dsthrfd. dst ending time is controlled by dstmorv, dstdwrv, dstdtrv and dsthrrv. the following tables describe the structure and functions of the dstcr. dst forward registers (20h to 23h) dste is the dst enabling bit loca ted in bit 7 of register 20h (dstmofdxx). set dste = 1 will enable the dste function. upon powering up for the first time (including battery), the dste bit defaults to ?0?. the beginning of dst is controlled by the following dst registers. dstmofd sets the month that dst starts. the default value for the dst begin month is april (04h) . dstdw sets the day of the week that dst starts. dstdwfde sets the priority of the day of the week over the date. for dstdwfde=1, day of the week is the priority. note that day of the week counts from 0 to 6, like the rtc registers. the default for the dst forward day of the week is sunday (80h). dstdtfd control which date dst begins. the defaulted value for dst date is on the first date of the month. dstdtfd is only effective if dstdwfde = 0. dsthrfd controls the hour that dst begins. it includes the mil bit which is in the corresponding rtc register. these two registers need to match formats (military or am/pm) in order for the dst function to work. the default value for dst hour is 2:00am. the time is advanced from 2:00:00am to 3:00:00am for this setting. dst reverse registers (24h to 27h) the end of dst is controlled by the following dst registers. dstmorv sets the month that dst ends. the default value for the dst end month is october (10h). dstdwrv controls which count of the day of the week that dst should end. dstdwrve sets the priority of the day of the week over the date. for dstdwrve = 1, day of the week is the priority. note that day of the week counts from 0 to 6, like the rtc registers. the default for dst end is sunday (80h). dstdtrv controls which date dst ends. the default value dst is set to end is the first date of the month. the dstdtrv is only effective if the dstdwrve = 0. dsthrrv controls the hour that dst ends. it includes the mil bit which is in the corresponding rtc register. these two registers need to match formats (military or am/pm) in order for the dst function to work. the default value sets the dst end at 2:00am. the time is set back from 2:00:00am to 1:00:00am for this setting. table 20. dst forward registers name76543210 dstmofd dste not used not used dstmofd20 dstmofd13 dstmofd12 dstmofd11 dstmofd10 dstdwfd dstdwfde not used not used not used no t used dstdwfd12 dstdwfd11 dstdwfd10 dstdtfd not used not used dstdtfd21 dstdtfd20 dstdtfd13 dstdtfd12 dstdtfd11 dstdtfd10 dsthrfd mil not used dsthrfd21 dsthrfd20 dsthrfd13 dsthrfd12 dsthrfd11 dsthrfd10 table 21. dst reverse registers name 76543210 dstmorv not used not used not used dstmorv20 dstmorv1 3 dstmorv1 2 dstmorv1 1 dstmorv1 0 dstdwrv dstdwrve not used not used not used no t used dstdwrv12 dstdwrv11 dstdwrv10 dstdtrv not used not used dstdtrv 21 dstdtrv 20 dstdtrv1 3 dstdtrv1 2 dstdtrv1 1 dstdtrv1 0 dsthrrv mil not used dsthrrv 21 dsthrrv20 dsthrrv1 3 dsthrrv1 2 dsthrrv1 1 dsthrrv1 0 ISL12020
20 fn6450.0 march 29, 2007 temp registers (temp) the temperature sensor prod uces an analog voltage output and is input to an a/d converter which outputs a 10-bit temperature value in degrees ke lvin. the output is coded to produce greater resolution for the temperature control. tk07:00 are the lsbs of th e code, and tk09:08 are the msbs of the code. the output code can be converted to degrees centigrade by first converting from binary to decimal and then subtracting 369d. the practical range for the temp sensor register output is from 658d to 908d, or -40c to +85c. the tse bit must be set to ?1? to enable temperature sensing. user registers (acces sed by using slave address 1010111x) addresses [00h to 7fh] these registers are 128 bytes of battery-backed user sram. i 2 c serial interface the ISL12020 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive op erations. therefore, the ISL12020 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 7). on power up of the ISL12020, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the ISL12020 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 7). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 7). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 8). the ISL12020 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an address byte. the ISL12020 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation. table 22. 76543210 tk0l tk07 tk06 tk05 tk04 tk03 tk02 tk01 tk00 tk0m000000tk09tk08 temperature in c [(tk <9:0>)/2] - 369 = (eq. 1) figure 7. valid data changes, start and stop conditions sda scl start data data stop stable change data stable ISL12020
21 fn6450.0 march 29, 2007 device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifier. these bits are ?1101111? for the rtc registers and: 1010111? for the user sram. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 10). after loading the entire slave address byte from the sda bus, the ISL12020 compares the device identifier and device select bits with ?1101111? or ?1010111?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the 1 word address bytes as shown in figure 12. in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the control/stat us registers, the slave byte must be ?1101111x? in both places. write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL12020 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a three byte instruction followed by one or more data bytes (see figure 12). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the ISL12020 responds with an ack. then figure 8. acknowledge response from receiver figure 9. byte write sequence (slave address for csr shown) sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte data byte a c k signals from the master signals from the ISL12020 a c k 10 0 11 a c k write signal at sda 0000 111 address byte figure 10. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address ISL12020
22 fn6450.0 march 29, 2007 the ISL12020 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 12). the data bytes are from the memory location indicated by an internal pointer. this pointers initial value is determined by the address byte in the re ad operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 13h, the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. application section battery backup details note that any input signal conditioning circuitry that is added in regular operation or battery backup should have minimum supply current drain, or have t he capability to be put in a low power standby mode. op amps such as the el8176 have low normal supply current (50a) and standby power drain (3a ) , so can be used in battery backup applications. oscillator crys tal requirements the ISL12020 uses a standard 32.768khz crystal. either through hole or surface mount crystals can be used. table 23 lists some recommended surface mount crystals and the parameters of each. this list is not exhaustive and other surface mount devices can be used with the ISL12020 if their specifications are very similar to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent series resistance of less than 50k. the crystal?s temperature range specification should match the application. many crystals are rated for -10c to +60c (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operating at low frequencies such as 32.768khz are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and insure accurate clocking. figure 11 shows a suggested layout for the ISL12020 device using a surface mount crystal. two main precautions should be followed: ? do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the osc illator circuit to cause misclocking. ? add a ground trace around the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vicinity of the rtc device. table 23. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 figure 11. suggested layout for ISL12020 and crystal figure 12. read sequence (csr slave address shown) signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11 ISL12020
23 fn6450.0 march 29, 2007 in addition, it is a good idea to avoid a ground plane under the x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. if the ~irq/f out pin is used as a clock, it should be routed away from the rtc device as well. the traces for the vbat and vdd pins can be treated as a ground, and should be routed around the crystal. super capacitor backup the ISL12020 device provides a vbat pin which is used for a battery backup input. a super capacitor can be used as an alternative to a battery in cases where shorter backup times are required. since the battery backup supply current required by the ISL12020 is extremely low, it is possible to get months of backup operation using a super capacitor. typical capacitor values are a few f to 1f or more depending on the application. if backup is only needed for a few minutes, then a small inexpensive electrolytic capacitor can be used. for extended periods, a low leakage, high capacity super capacitor is the best choice. these devices are available from such vendors as panasonic and murata. the main specifications include working voltage and leakage current. if the application is for charging the capacitor from a +5v 5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5v to slightly over 5.0v. a capacitor with a rated wv of 5.0v may have a reduced lifetime if the supply voltage is slightly high. the leakage current should be as small as possible. for example, a super capacitor should be specified with leakage of well below 1a. a standard electrolytic capacitor with dc leakage current in the microamps will have a severely shorte ned backup time. following are some examples with equations to assist with calculating backup times and required capacitance for the ISL12020 device. the backup supply current plays a major part in these equations, and a typical value was chosen for example purposes. for a robust design, a margin of 30% should be included to cover supply current and capacitance tolerances over the results of the calculations. even more margin should be included if periods of very warm temperature operat ion are expected. example 1. calculating backup time given voltages and capacitor value in figure 13, use c bat = 0.47f and v dd = 5.0v. with v dd = 5.0v, the voltage at v bat will approach 4.7v as the diode turns off completely. the ISL12020 is specified to operate down to v bat = 1.8v. the capacitance charge/discharge equation is used to estimate the total backup time: rearranging gives c bat is the backup capacitance and dv is the change in voltage from fully charged to loss of operation. note that i tot is the total of the supply current of the ISL12020 (i bat ) plus the leakage current of the capacitor and the diode, i lkg . in these calculations, i lkg is assumed to be extremely small and will be ignored. if an application requires extended operation at temperat ures over +50c, these leakages will increase and hence reduce backup time. note that i bat changes with v bat almost linearly. this allows us to make an approximation of i bat , using a value midway between the two endpoints. the typical linear equation for i bat vs v bat is: using this equation to solve for the average current given 2 voltage points gives: combining with equation 3 gives the equation for backup time: where c bat = 0.47f v bat2 = 4.7v v bat1 = 1.8v i lkg = 0 (assumed minimal) solving equation 5 for this example, i batavg = 4.387e-7a t backup = 0.47*(2.9)/4.38e-7 = 3.107e6s since there are 86,400 seconds in a day, this corresponds to 35.96 days. if the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be: i = c bat *dv/dt (eq. 2) dt = c bat *dv/i tot to solve for backup time. (eq. 3) i bat = 1.031e-7*(v bat ) + 1.036e-7a (eq. 4) i batavg = 5.155e-8*(v bat2 + v bat1 ) + 1.036e-7a (eq. 5) t backup = c bat *(v bat2 - v bat1 ) / (i batavg + i lkg ) (eq. 6) seconds c bat = 0.70*35.96 = 25.2 days (eq. 7) figure 13. supercapacitor charging circuit 2.7v to 5.5v v dd v bat gnd 1n4148 c bat ISL12020
24 fn6450.0 march 29, 2007 example 2. calculating a capacitor value for a given backup time referring to figure 13 again, the capacitor value needs to be calculated to give 2 months (60 days) of backup time, given v dd = 5.0v. as in example 1, the v bat voltage will vary from 4.7v down to 1.8v. we will need to rearrange equation 3 to solve for capacitance: using the terms described above, this equation becomes: where t backup = 60 days*86, 400s/day = 5.18 e6s i batavg = 4.387 e-7a (same as example 1) i lkg = 0 (assumed) v bat2 = 4.7v v bat1 = 1.8v solving gives c bat = 5.18 e6 * (4.387 e-7)/(2.9) = 0.784f if the 30% tolerance is included for tolerances, then worst case cap value would be: c bat = 1.3 *.784 = 1.02f c bat = dt*i/dv (eq. 8) c bat = t backup *(i batavg + i lkg )/(v bat2 ? v bat1 ) (eq. 9) ISL12020
25 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6450.0 march 29, 2007 ISL12020 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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